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this is information on a product in full production. january 2013 doc id 022111 rev 6 1/25 1 stm6519 4-pin smart reset? datasheet - production data features operating voltage range 2 v to 5.5 v low supply current 1 a integrated test mode single smart reset? push-button input with fixed extended reset setup delay (t src ) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal input pull-up resistor push-button controlled reset pulse duration ? option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed ? option 2: defined output reset pulse duration (t rec ), factory-programmed single reset output ? active-low or active-high ? push-pull or open drain with optional pull-up resistor fixed smart reset input logic voltage levels operating temperature: -40 c to +85 c udfn4 package 1.00 mm x 1.45 mm and udfn6 package 1.00 mm x 1.45 mm ecopack ? 2 (rohs compliant, halogen- free) applications mobile phones, smartphones, pdas e-books mp3 players games portable navigation devices any application that requires delayed reset push-button response for improved system stability udfn6 1.00 mm x 1.45 mm udfn4 1.00 mm x 1.45 mm www.st.com
contents stm6519 2/25 doc id 022111 rev 6 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 power supply (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 smart reset input (sr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 reset output (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.6 rst output undervoltage behavior (for open-drain option) . . . . . . . . . . . . 8 4 typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
stm6519 list of tables doc id 022111 rev 6 3/25 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. udfn4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package mechanical data . . . . . 18 table 6. udfn6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package mechanical data . . . . . 19 table 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
list of figures stm6519 4/25 doc id 022111 rev 6 list of figures figure 1. stm6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. udfn4 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. udfn6 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. stm6519 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. typical application diagram - input, output and stm6519 device in one voltage domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. typical application diagram - stm6519 device in a different voltage domain than input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. typical application diagram in different voltage domains - sr input in v bat domain like v cc totally disables the test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. rst output without t rec option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. rst output with t rec option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. supply current (i cc ) vs. temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. smart reset delay (t src ) vs. temperature (t a ), t src = 4.0 s (typ.) . . . . . . . . . . . . . . . . . . 12 figure 12. test mode entry voltage (v test ) vs. temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. initial test mode time (t src-ini ) vs. temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. udfn4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline . . . . . . . . . . . . . 17 figure 15. footprint recommendation for udfn4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch . . 18 figure 16. udfn6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline . . . . . . . . . . . . . 19 figure 17. footprint recommendation for udfn6 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch. . . 20 figure 18. carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
stm6519 description doc id 022111 rev 6 5/25 1 description the smart reset tm devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. this is done by implementing an extended smart reset input delay time (t src ), which ensures a safe reset and eliminates the need for a specific dedicated reset button. this reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. when the input push-button is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. if the system still does not respond pro perly, continuing to keep the push-buttons closed for the extended setup time t src causes a hard reset of the processor through the reset output. the stm6519 has one smart reset input (sr ) with preset delayed smart reset setup time (t src ). the reset output (rst ) is asserted after the smart reset input is held active for the selected t src delay time. the rst output remains asserted either until the sr input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for t rec (i.e. factory-programmed). the device fully operates over a broad v cc range from 2.0 v to 5.5 v. 1.1 test mode after pulling sr up to v test (v cc + 1.4 v) or above, the counter starts to count the initial shortened t src-ini (42 ms, typ.). after t src-ini expires, the rst output either goes down for t rec (if t rec option is used) or stays low as long as overvoltage on sr is detected (if t rec option is not used). this is feedback, and the user only knows that the device is locked in test mode. each time the sr input is connected to ground in test mode, a shortened t src-short (t src /128) is used instead of regular t src (0.5 s - 10 s). in this way the device can be quickly tested without repeating test mode triggering. return to normal mode is possible by performing a new startup of the device (i.e. v cc goes to 0 v and back to its original state). the advantages of this solution are its high glitch immunity, user feedback regarding entry into test mode, and testability within the full v cc range.
description stm6519 6/25 doc id 022111 rev 6 1.2 logic diagram figure 1. stm6519 logic diagram 1.3 pin connections figure 2. udfn4 pin connections (top view) figure 3. udfn6 pin connections (top view) 1. not connected (not bonded); should be connected to v ss . 34- 234 '.$ 6 ## 32 !- 6 33 32 6 ## 234 5$&. 34- !- 6 33 .# 32 6 ## 234 5$&. .# 34- !-6
stm6519 device overview doc id 022111 rev 6 7/25 2 device overview figure 4. stm6519 block diagram table 1. signal names pin number name type description udfn6 udfn4 14rst output reset output, active-low, open drain. 21v ss supply ground ground 32sr input smart reset input, active-low. 43v cc supply voltage positive supply voltage for the device. a 0.1 f decoupling ceramic capacitor is recommended to be connected between v cc and v ss pins. 5 - nc - not connected (not bonded); should be connected to v ss . 6 - nc - not connected (not bonded); should be connected to v ss . 32 t 32# generator t 2%# generator 234 /vervoltagedetect testmodetrigger !-6 optional
pin descriptions stm6519 8/25 doc id 022111 rev 6 3 pin descriptions 3.1 power supply (v cc ) this pin is used to provide power to the smart reset device. a 0.1 f ceramic decoupling capacitor is recommended to be connected between the v cc and v ss pins, as close to the stm6519 device as possible. 3.2 power-up sequence in normal mode, if different input side (sr ) and v cc voltage domains are used, power-on sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode entry: there should not be logic high present on the sr input before the v cc power-up. however v cc and v(sr ) rising at the same time is ok (e.g. if both are in the same voltage domain), the device will then safely start into normal operating mode, with rst output inactive (in high-z mode for open-drain option). 3.3 ground (v ss ) this is the ground pin for the device. 3.4 smart reset input (sr ) push-button smart reset input, active-low with optional pull-up resistor. sr input needs to be asserted for at least t src to assert the reset output (rst ). by connecting a voltage higher than v cc + 1.4 v to the sr input the device enters test mode (see section 1: description on page 5 for more information). 3.5 reset output (rst ) rst is active-low or active-high, open drain or push-pull reset output with optional internal pull-up resistor. output reset pulse width is optional as follows: neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert) fixed, factory-programmed output reset pulse duration for t rec independent on smart reset input state. 3.6 rst output undervoltage behavior (for open-drain option) high-z on rst output below the specified operating voltage range is guaranteed at v cc power-on or in case that valid v cc dropped while the device was idle, i.e. while both output and input were inactive.
stm6519 typical application diagrams doc id 022111 rev 6 9/25 4 typical application diagrams figure 5. typical application diagram - input, output and stm6519 device in one voltage domain figure 6. typical application diagram - stm6519 device in a different voltage domain than input and output 1. open-drain rst output type and fixed sr input logic threshold allows to use the device in different voltage domains. to prevent entering test mode by creating a condition v(sr ) > v cc + 1.1 v typ., v cc should be powered up before or together with voltage on the sr input.
typical application diagrams stm6519 10/25 doc id 022111 rev 6 figure 7. typical application diagram in different voltage domains - sr input in v bat domain like v cc totally disables the test mode
stm6519 timing diagrams doc id 022111 rev 6 11/25 5 timing diagrams figure 8. rst output without t rec option 1. v cc should be powered up before or together with voltage on the sr input to prevent entering test mode by creating a condition v(sr ) > v cc +1.1 v typ. figure 9. rst output with t rec option 1. v cc should be powered up before or together with voltage on the sr input to prevent entering test mode by creating a condition v(sr ) > v cc +1.1 v typ.
typical operating characteristics stm6519 12/25 doc id 022111 rev 6 6 typical operating characteristics figure 10. supply current (i cc ) vs. temperature (t a ) figure 11. smart reset delay (t src ) vs. temperature (t a ), t src = 4.0 s (typ.) !- 4emperature4 ! ?# 6 ## 6 6 ## 6 6 ## 6 4emperature4 ! ?# 3mart2esetdelayt 32# s 6 ## 6 6 ## 6 6 ## 6 !-
stm6519 typical operating characteristics doc id 022111 rev 6 13/25 figure 12. test mode entry voltage (v test ) vs. temperature (t a ) figure 13. initial test mode time (t src-ini ) vs. temperature (t a ) 4emperature4 ! ?# 4estmodeentryvoltage6 4%34 6 6 ## 6 6 ## 6 6 ## 6 !- 4emperature4 ! ?# )nitialtestmodetimet 32#?).) ms 6 ## 6 6 ## 6 6 ## 6 !-
maximum ratings stm6519 14/25 doc id 022111 rev 6 7 maximum ratings stressing the device above the rating listed in table 2: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in table 3: operating and measurement conditions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics? sure program and other relevant quality documents. table 2. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off) -55 to +150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltage -0.3 to 5.5 v v cc supply voltage -0.3 to 7 v esd v hbm electrostatic discharge protection, human body model (jesd22- a114-b level 2) 2kv v rcdm electrostatic discharge protection, charged device model, all pins 1 kv v mm electrostatic discharge protection, machine model, all pins (jesd22-a115-a level a) 200 v latch-up (v cc pin, sr reset input pin) eia/jesd78
stm6519 dc and ac parameters doc id 022111 rev 6 15/25 8 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in table 4: dc and ac characteristics are derived from tests performed under the measurement conditions summarized in table 3: operating and measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 3. operating and measurement conditions symbol parameter value unit v cc supply voltage 2.0 to 5.5 v t a ambient operating temperature -40 to +85 c t r , t f input rise and fall times 5ns input pulse voltages 0.2 to 0.8 v cc v input and output timing reference voltages 0.3 to 0.7 v cc v
dc and ac parameters stm6519 16/25 doc id 022111 rev 6 table 4. dc and ac characteristics symbol parameter test conditions (1) min. typ. (2) max. unit v cc supply voltage 2.0 5.5 v i cc supply current sr = v cc , t rec and t src counter is not running 0.4 1.0 a v ol reset output voltage low v cc 4.5 v, sinking 3.2 ma 0.3 v v cc 3.3 v, sinking 2.5 ma 0.3 v v cc 2.0 v, sinking 1 ma 0.3 v t rec reset timeout delay, factory-programmed (device option) 0.85 1.28 1.71 ms 66 100 134 ms 140 210 280 ms 240 360 480 ms r puo internal output pull-up resistor on rst (device option) 65 k i lo output leakage current v rst = 5.5 v, open drain device option without output pull-up resistor -0.1 0.1 a smart reset t src smart reset delay t a = -40 to +85 c 0.8 x t src t src (3) 1.2 x t src s t a = 25 c 0.9 x t src 1.1 x t src v il sr input voltage low v ss -0.3 0.3 v v ih sr input voltage high 0.85 5.5 v r pui internal input pull-up resistor on sr (device option) 65 k i leak sr input leakage current device option without input pull-up resistor -0.1 0.1 a input glitch immunity t src s test mode v test test mode entry voltage v cc +0.9 v cc +1.1 v cc +1.4 v t src-ini initial test mode time 28 42 56 ms t src-short shortened smart reset delay t src / 128 ms 1. valid for ambient operating temperature t a = -40 to +85 c, v cc = 2.0 to 5.5 v. 2. typical values are at 25 c and v cc = 3.3 v unless otherwise noted. 3. factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps.
stm6519 package information doc id 022111 rev 6 17/25 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 14. udfn4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline 5$&.
package information stm6519 18/25 doc id 022111 rev 6 figure 15. footprint recommendation for udfn4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch table 5. udfn4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package mechanical data symbol dimensions note (1) 1. controlling dimension: millimeters. (mm) (inches) min. typ. max. min. typ. max. a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 0.02 0.05 0.000 0.001 0.002 a3 0.127 0.005 b 0.20 0.25 0.30 0.008 0.010 0.012 d 1.40 1.45 1.50 0.055 0.057 0.059 e 0.95 1.0 1.05 0.037 0.039 0.041 e 0.65 0.026 l 0.30 0.35 0.40 0.012 0.014 0.016 n 44 !-
stm6519 package information doc id 022111 rev 6 19/25 figure 16. udfn6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline table 6. udfn6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package mechanical data symbol dimensions note (1) 1. package outline exclusive of any mold flashes dimensions and metal burrs. (mm) (inches) min. typ. max. min. typ. max. a 0.50 0.55 0.60 0.0197 0.0217 0.0236 a1 0.00 0.02 0.05 0.000 0.0008 0.0020 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 d 1.40 1.45 1.50 0.0551 0.0571 0.0591 e 0.95 1.00 1.05 0.0374 0.0394 0.0413 e 0.45 0.50 0.55 0.0177 0.0197 0.0217 k 0.20 0.0079 l 0.30 0.35 0.40 0.0118 0.0138 0.0157 5$&. , . $ % ! ! , k eb
package information stm6519 20/25 doc id 022111 rev 6 figure 17. footprint recommendation for udfn6 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch !-
stm6519 tape and reel information doc id 022111 rev 6 21/25 10 tape and reel information figure 18. carrier tape 1. 10-sprocket hole pitch cumulative tolerance 0.20. figure 19. pin 1 orientation !- !-6 5serdirectionoffeed
part numbering stm6519 22/25 doc id 022111 rev 6 11 part numbering table 7. ordering information scheme example: stm6519 a h a r ub 6 f device type stm6519 reset (v cc monitoring threshold) voltage v rst a = no v cc monitoring feature smart reset setup delay (t src ) (1) 1. smart reset delay (t src ) is available from 0.5 s to 10 s in 0.5 s steps (typ.). minimum order quantities may apply. contact local sales office for availability. c = factory programmable t src = 1.5 s (typ.) h = factory programmable t src = 4.0 s (typ.) l = factory programmable t src = 6.0 s (typ.) p = factory programmable t src = 7.5 s (typ.) u = factory programmable t src = 10.0 s (typ.) inputs, outputs type (2) 2. push-pull reset output type also available (active-low or active-high). sr input and open drain reset output available with optional pull-up resistor. minimum order quantities may apply. contact local sales office for availability. a = active-low sr input with no pull-up, active-low open drain rst output with no pull-up b = active-low sr input with pull-up, active-low open drain rst output with no pull-up reset timeout period (t rec ) a = factory programmable t rec = 210 ms (typ.) b = factory programmable t rec = 360 ms (typ.) e = factory programmable t rec = 1.28 ms (typ.) f = factory programmable t rec = 100 ms (typ.) r = push-button controlled (no defined t rec ) package uc = udfn-4l ub = udfn-6l temperature range 6 = -40 c to +85 c shipping method f = tape and reel
stm6519 package marking information doc id 022111 rev 6 23/25 12 package marking information figure 20. package marking (top view) table 8. package marking part number t src (s) smart reset inputs (1) 1. al = active-low. output type (2) 2. od = open drain, al = active-low. t rec option (3) 3. no t rec = push-button controlled reset pulse width, any other value represents typical value of t rec . package topmark stm6519aharuc6f 4.0 al od, al no t rec udfn4 ha stm6519alaruc6f 6.0 al od, al no t rec udfn4 la stm6519aparuc6f 7.5 al od, al no t rec udfn4 pa stm6519auaruc6f 10.0 al od, al no t rec udfn4 ua STM6519ACARUB6F 1.5 al od, al no t rec udfn6 ca stm6519aharub6f 4.0 al od, al no t rec udfn6 ha stm6519alarub6f 6.0 al od, al no t rec udfn6 la stm6519apaaub6f 7.5 al od, al 210 ms udfn6 pb stm6519aparub6f 7.5 al od, al no t rec udfn6 pa stm6519apbbub6f 7.5 al + pull-up od, al 360 ms udfn6 pc stm6519auarub6f 10.0 al od, al no t rec udfn6 ua ! " !dotpinreference "markingareatopmark '!0-3-$
revision history stm6519 24/25 doc id 022111 rev 6 13 revision history table 9. document revision history date revision changes 12-aug-2011 1 initial release. 22-sep-2011 2 updated figure 5 , ta b l e 4 , table 7 and table 8 . 07-oct-2011 3 removed label ?preliminary data?. 27-oct-2011 4 updated figure 3 and table 1 . 13-jun-2012 5 updated features , ta b l e 4 , title of section 9 . 17-jan-2013 6 moved figure 4 below ta ble 1 . added section 3.2 , section 3.6 , figure 6 and figure 7 . updated title of figure 5 . updated figure 8 and figure 9 (added notes and minor modifications).
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